AW

Aarav Wattal

MTS @ Etched | EE+CS @ Stanford | prev. NVIDIA, AMD, Majestic Labs

San Francisco Bay Area · 2 connections

NVIDIA

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About

I build AI-native hardware systems at the intersection of memory, compilers, and silicon architecture. My work spans memory controller verification at AMD, ML compiler development at Majestic Labs, and hardware-software co-design research at Stanford. I’m particularly interested in breaking the memory wall and building infrastructure for the next generation of AI accelerators. Reach out at awattal [at] stanford [dot] edu

Experience

GPU C2C Interconnect Design Verification Engineer InternNVIDIA
Jun 2026 to Sep 2026
Undergraduate Researcher (Hardware Accelerators + HW/SW Codesign)Department of Electrical Engineering, Stanford University Basic company page — company details not listed yet
Jan 2025 to Dec 2025
Memory Hardware Researcher (First Author, IEEE SISPAD 2023)Department of Electrical Engineering, Stanford University Basic company page — company details not listed yet
Mar 2021 to Nov 2023
Design Verification Engineer Intern (HBM/GDDR7 Memory Controllers)AMD
Jun 2025 to Sep 2025
Machine Learning Engineer InternReazon Holdings, inc. Basic company page — company details not listed yet
Jun 2024 to Sep 2024
Member of Technical Staff (ASIC)Etched Basic company page — company details not listed yet
Sep 2026
First Place Grand PrizeTreeHacks
Feb 2024 to Feb 2024
Independent iOS Engineer (Contract)Various Companies Basic company page — company details not listed yet
Aug 2019 to Jan 2024
Software Engineer InternCisco
Jul 2021 to Aug 2021

Education

Stanford University
Bachelor of Science - BS, Electrical Engineering, Computer Science
Stanford University
Bachelor of Science - BS Electrical Engineering, Computer Science